...To get the 2 bytes into the RAM it would go Low byte then High byte, or is it the same as addressing with High byte first then low byte ?...
You got it. Low Byte 1st because in a Little Endian processor, as Intels are, the lower byte goes in the lower RAM address value. This assumes you are writing using the DAR. I don't know if SPC writes are ever done by the processor since you really don't have control over whether the processor does SPC or DAR writes from the programming level. SPC, as far as I know it, is only instructions (operands and opcodes) and DAR is only fetching data. It's almost Harvard-centric on a VonNeumann architecture. For those non-CS majors out there reading that, Harvard and VonNeumann are computer memory architectures. Google them for more details.
...Are the Ram writes addressable through both the SPC and DAR counters ?...
Answered above before I even read this question. But to be explicit, my answer is I don't know. However from all the conversation I've had with Craig about what he's seen via scope, SPC is only used for reads. That doesn't mean it is never writing. It just means if it is, it's not known. It would be nice to know for sure.
...Also can we write odd bytes only?...
Yes and no. Conceptually, you can. But in reality, no. The way the processor does this is when you make a single byte write to an odd address, the processor must fetch the even address before performing the 2-byte DAR write which always starts with the even address. Since it cannot write directly to odd address without 1st writing to the even, it needs the existing value of the even byte so it doesn't tromple it while updating the odd byte of a word.
...I may have to run some experiments to get the full picture.
Good luck. I'd love to see some good scope or logic analyzer feedback to put some clarification on this. It seems the only people that know this stuff are the people that build hardware for the MBus and thus need to know it. It may be documented somewhere, I just haven't found it. I would say look int he 8096 docs, but the 8096 memory architecture is different than the 8061/5, so I don't know that it would apply.
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