Search found 479 matches

by tvrfan
Sat Feb 15, 2020 4:30 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

SAD bugs in 4.0.4

Just a note for users of SAD - Am working on data cleanups and table/function sizes/layouts/ends, which don't always work correctly. I've found a couple of bugs to fix....may find some more.......... 1) indexed instruction prints sometimes drop the register part of the index in the pseudo code, and ...
by tvrfan
Thu Feb 13, 2020 7:41 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

Pym's SAD806x source is posted on OpenEEC if you want to poke through it. He's got some handy utilities built in to that tool. thanks - But now my inner dinosaur comes out... How do I compile c# on linux ?? Ummmm....... :oops: <short delay whilst frantic typing noises happen>...Damn, this stuff is ...
by tvrfan
Tue Feb 11, 2020 1:43 pm
Forum: EECGeeks
Topic: quick question about indexed ops
Replies: 7
Views: 191

Re: quick question about indexed ops

Bob, Yep, No worries. I was checking that perhaps a non-zero register with long index might possibly be signed, but that xdt2 example shows it's not. All good. Thanks for that piece of info about the RAM, it explains what's going on in the code, I thought RAM/KAM was always below 0x2000. I now see t...
by tvrfan
Tue Feb 11, 2020 4:39 am
Forum: EECGeeks
Topic: quick question about indexed ops
Replies: 7
Views: 191

Re: quick question about indexed ops

If the 2nd byte of the instruction is even then it is short indexed, if the 2nd byte is odd then it is long indexed. I can only recall seeing the zero register being used with long indexing and it's an unsigned index. Thanks Bob. But you do see long indexes with non-zero register here and there as ...
by tvrfan
Mon Feb 10, 2020 11:53 pm
Forum: EECGeeks
Topic: quick question about indexed ops
Replies: 7
Views: 191

Re: quick question about indexed ops

Having dug around for info and thought about it... It looks like it may be that - Short index is SIGNED (A9L for proof) Long index is SIGNED ?? (Guess) Zero index (short and long) is UNSIGNED. This would explain why it has a separate section in the 8096 manual, when it's really just using R0. And it...
by tvrfan
Mon Feb 10, 2020 9:02 pm
Forum: EECGeeks
Topic: quick question about indexed ops
Replies: 7
Views: 191

quick question about indexed ops

Experts help please ! This is from BWAK3N2 - (8065 multibank with 4 banks) I found these when looking for a different bug. 8ce34: c3,01,98,f2,44 stw R44,[R0+f298] ..also... 8cdd8: a3,01,98,f2,34 ldw R34,[R0+f298] 8cddd: b3,01,a3,f2,46 ldb R46,[R0+f2a3] 8cd86: b3,01,96,f2,46 ldb R46,[R0+f296] 8cd8b: ...
by tvrfan
Sat Feb 08, 2020 3:23 am
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

jsa, I see that the DADS bin eludes SAD completely for data items. I've seen this in a few places in xdt2, where several funcs are referred to via a small list with a register as an index, but DADS seems to do EVERYTHING from preset registers which are NOT setup via the 'standard' rbase mechanism. O...
by tvrfan
Fri Feb 07, 2020 2:25 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

Thanks John, At the moment, I am looking at ways to 1. Expand the ends of the 1D functions correctly. Easy if end rows are not all zero. 2. Find a better way to get rows x cols for 2D tables. Trying out a 'least differences' approach which seems to have promise. Have noted that SAD sometimes gets th...
by tvrfan
Fri Jan 31, 2020 5:41 pm
Forum: EECGeeks
Topic: ROM1 address
Replies: 19
Views: 561

Re: ROM1 address

I have a practical viewpoint............ Putting that checksum value near the front makes ALL changes (i.e. different versions) immediately obvious to anyone looking at it..........so makes sense for that purpose, rather than 'hiding' it in a load of other values. I guess the same would be true it i...
by tvrfan
Mon Jan 20, 2020 2:09 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD 4.0.4

Ah, right. I was thinking more of home or office type desktop - not industrial control type stuff. A quick scan of your acronyms shows there are some alternatives, but yeah, how good they are remains the question. So you will be stuck with either a VM (VirtualBox is very good though) or something li...
by tvrfan
Sat Jan 18, 2020 9:11 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD 4.0.4

Linux - Software packages ? Like what ? (I'm interested) As far as I am aware there's actually not that much left which doesn't have a linux equivalent (and the linux one will typically read the original Win files too, e.g. LibreOffice ). But then stuff like MS virtual C won't just swop over.... I'v...
by tvrfan
Tue Jan 14, 2020 11:51 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

SAD 4.0.4 released

As per release notes - 1. Changed vector list (=pointer list) validation YET AGAIN after discovering another couple of bins which don't work. added a simpler, but new rule to validate whether list is real. 2. Added extra scan pass to check for 'code holes' which may have been missed. Example is wher...
by tvrfan
Sat Jan 04, 2020 3:01 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

Good luck ! I gave up fighting with Windows a long while ago, and went Linux instead, and am trying to convince as many people as possible to do the same. (Yeah, I know, but I can't help pushing at least a little bit ! ) I have XP and 7 only in virtual machines (VirtualBox), used mostly for SAD buil...
by tvrfan
Fri Jan 03, 2020 10:48 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

SAD 4.0.3.d

OK, I hope that's fixed the symbols. I couldn't actually reproduce the issue with user defined names being replaced with SAD 'auto' ones, but I did find an error with finding symbols with ranges defined, which may have caused a range of problems. Tidied up and fixed symbol names for 'if' statements,...
by tvrfan
Tue Dec 31, 2019 2:29 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

OK. good. I've come up with these rules for bit flags (applied in order) - 1. If a sym is defined for the relevant bit, either as even address and bit > 7, or as odd address and bit < 8, that name will always appear. (which implies convert to byte where required) 2. if a sym is defined for the byte ...
by tvrfan
Tue Dec 31, 2019 4:02 am
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

Thanks for that ---- I'll save it and read several times over and have a think about it. Trouble is it all gets very complicated. I did wonder about keeping a calculation 'memory' for some groups of opcodes. Incidentally, only DIV and MLT have 32 bit (LONG) operations, shifts can be regarded as subs...
by tvrfan
Mon Dec 30, 2019 7:29 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

thanks John. Noted for checking... BUT .... A question prompted by the bits change in style --> B8_R34 to B0_R35. I'm looking at my bits change, and I have forgotten to recheck the symbol names properly, which is why it isn't showing up correctly (per jsa post) But this makes me ask the question.......
by tvrfan
Mon Dec 30, 2019 5:37 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

OK, well I agree that's a lot better - I have broken the "Bx_wholename" with my bit change. OK. Ah. I think I know why already on this one....... I have changed the Bx_Rn for split byte.... looks like somewhere SAD still overrides a user defined sym - OK. need to look for this one. two to look at th...
by tvrfan
Mon Dec 30, 2019 1:33 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD 4.0.3c released

Hopefully, this will finally fix up symbols and rbases with ranges (and bit syms). Error was in the command handling where cmd has a single start address combined with a range (i.e. start-end address pair). Also changed Bx_Rn to byte, as per request. It's still a debate about the ldx ops - in some b...
by tvrfan
Mon Dec 30, 2019 4:31 am
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

Symbols all f**ked up, after making a change for a multibank error. Found it. Another stupid mistake.
so ifs, and some bit names don't work.

Will change the ands and ors to byte too, I'll see if I can get ldb and ldw to work with flags too...
by tvrfan
Sun Dec 29, 2019 11:24 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

Yep, I spotted that bit issue on something else - I've screwed up a 'whole name' (byte or word) versus a 'bit name' storage somewhere..... back soon. Hey, and thanks again for being my tester - these are all well spotted, and I'm too close to see some of the stuff you are seeing... Great stuff. I di...
by tvrfan
Sun Dec 29, 2019 10:53 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

Ah, I see, 57d2: b1,06,5a ldb R5a,6 R5a = 6; 57d5: 71,f7,ea an2b Rea,f7 B3_Rea = 0; 57d8: 36,de,06 jnb B6,Rde,57e1 if (B6_Rde = 1) { 57db: 91,08,ea orb Rea,8 B3_Rea = 1; 57de: 95,10,5a xorb R5a,10 B4_R5a ^= 1; } That ldb could be shown in the flags style too................hmmm.... I need to work on...
by tvrfan
Sun Dec 29, 2019 10:47 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

Not surprised, what the hell is "R 0" ???? That's not in my syntax anywhere !! I need to go check that !! And just a reminder for the bits ops - those opcodes support indirect and indexed as well. It's perfectly legal to do R32 &= [R34]; and R32 &= [R34 + 6]; (ouch!!, but say in the injection table ...
by tvrfan
Sun Dec 29, 2019 10:14 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

Yes - can change that. Currently for a word op, it will show bits 0-15, and it always has (3.08 too). For a SYM name however, because B8 R34 = B0 R35, it internally stores those sym names as byte addresses with 0-7 as bit number. There is an extra check to convert it. That then shows the same SYM na...
by tvrfan
Sun Dec 29, 2019 3:22 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD 4.0.3b released

Interim fixes for jsa's reported bugs released to git as 4.03b .... 1. Fix for 'return' being shown for a jump when it should not (and resultant incorrect braces being shown). 2. Change default rules for when individual bit updates are shown (i.e. "Bn_Rx = 0" style), more as 3.08 did. NB. ONLY appli...
by tvrfan
Sat Dec 28, 2019 2:17 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

thanks again. Yes agree - Anything which is a single bit will always be a single flag set or clear, BUT I'm pretty sure that I've seen AND Rx, 0xF0 done in a calculation, so I don't want to make that part worse. Or another way is to have a global option to set it on or off (by default that is - SYM ...
by tvrfan
Sat Dec 28, 2019 12:26 am
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

4.03a dir STR 52FF 5303 :Y N lst 52ff: 2d,2e scall 502f 502f(); 5301: 2f,30 scall 5233 5233(); 5303: 32 struct 32 Oops - default rule is that code ALWAYS supercedes data (as it's possible to get an indexed data pointer into a code area), and I have changed the way the code interacts (emulation agai...
by tvrfan
Fri Dec 27, 2019 10:31 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD disassembler progress

OK, thanks. Symbol Names I had to rewrite some of the analysis code to get emulation to work, and that meant changing where and when things like symbols are sorted, and for indirect and indexed, the code actually has to get the operand data correctly to emulate. SAD just got enough to print before v...
by tvrfan
Thu Dec 26, 2019 7:57 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD 4.0.3a released

Found two small bugs with subroutine commands already, if defined in .dir file.
Also have fixed bank commands, which now seem OK, but may still be a bug to be found, so still printing with comment at front.

have released update build under 4.0.3 (and commit is labelled "4.0.3a")
by tvrfan
Wed Dec 25, 2019 2:58 pm
Forum: EECGeeks
Topic: SAD disassembler progress
Replies: 161
Views: 8511

Re: SAD 4.0.3 released

Released 4.0.3 to github, main fixes are to allow sub commands to work, and sort out auto names. Also fixed a few other bugs as found. (see releases doc) Tested mainly on Linux , with quick test on Win XP to confirm all OK (CARD, A9L,XDT2, etc). Updated user manual to V4 to reflect command changes. ...