I feel like pointing out that the documentation says the registers are actually implemented as SRAM and refers to them as RAM banks, which is no doubt a source of confusion. And yes, it is crucial for this conversation to make a distinction between external and internal memories and not to confused the register file with external ram.
6-4 GENERAL REGISTER FILE (ON-BOARD RAM BANKS)
The 8065's on-board general register file is a keep-alive 491-word read/write static random
access memory (RAM) that is memory-mapped between addresses ^0024 thru ^03FF. To retain
the basic operand addressing scheme intrinsic to the instruction set common to all EEC-IV micro
processors, the general register file is divided into four RAM banks (RAM banks #0 thru #3).
What is the significance of a "single bank" 8065? I thought they are all capable
of memory expansion, which would be easy enough to test on the P3M with a test program and a multimeter, and this should have nothing to do with register "RAM bank" access.
In researching the hardware reference manual I made some observations, some of which have been covered before:
"Mask Options" are for external memories and refer to address masks.
A "Step" is also referred to as a "design level" as in " [...]the 8061 40-pin silicon design level step "D" Indicates the status of the[...]" "[...]This restriction is applicable to all 8061 silicon prior to step "D" level"[/list]
The table of part numbers indicates that in 1989 part numbers for the 8065 were still "TBD" yet the design level was already set to "D". That may mean that for all practical purposes "from step 'D'" applies to all production 8065s and would only not apply to engineering samples.
Design level step "D" 8065's were defective and did not perform direct word RAM bank access as documented. This was corrected in a later design revision. This has nothing to do with the DUCE address mask option "D".
Are there any 8065's produced before the one in P3M that are known to do direct work RAM bank switching as documented?
As I look through the hardware manual it is clear that information about the 8065 was preliminary. Part numbers are TBD, there is no section documenting the design levels are there are for other chips, and there are notes referring to the future such as
NOTE EITHER ADDRESS RANGE MASK OPTION "E"
OR AN ALTERNATE BANKING SCHEME WILL BE
DEFINED FOR RAM
You guys have way more experience looking at bins and EECs than I do so I will gladly accept evidence you have to the contrary, but my suspicion is that this difference in behavior was unintentional and it might be more accurate to say that the silicon was wrong than the documentation is wrong (and yes I know documentation is still wrong in places).
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