[jsa]

Do we agree that the P3M hardware box only has 1 ROM bank?

Yes, that has been stated many times.

Does the disassembler happen to know that with a 8065 with 1 rom bank, no rom bank switching, that a word direct odd address read, will not, and should not do any +100?

You've gone and done it again!
SF/R+100 is not expected to be RAM +100 or ROM+100.

Do you accept that ROM is read only memory external to the uP?

Do you accept non register RAM is read and write memory external to the uP?

Do you accept Special Function and General registers are internal to the 8065?

Are you implying that multi ROM Bank hardware working in Memory Expansion mode will apply +100 addressing offsets to external RAM and ROM?

edit; to make distinction between ram internal and external to uP.

[sailorbob]

Do you accept RAM banks are read and write memory external to the uP?

Did you mean to say:

Do you accept RAM banks are read and write memory internal to the uP?

[jsa]

Do you accept RAM banks are read and write memory external to the uP?

Did you mean to say:

Do you accept RAM banks are read and write memory internal to the uP?

No not quite. Drop the word bank.
Registers are the internal ram banks.

Do you accept RAM is read and write memory external to the uP?

[sailorbob]

The EEC has got RAM both internally on the 8061/5 and externally to the 8061/5. In the 8065 the internal RAM is organised in 4 banks and this comprises what is referred to as Special Function Registers and General Registers. I would not refer to any external RAM as being in banks as I have not seen any evidence of that.

[ollopa]

I feel like pointing out that the documentation says the registers are actually implemented as SRAM and refers to them as RAM banks, which is no doubt a source of confusion. And yes, it is crucial for this conversation to make a distinction between external and internal memories and not to confused the register file with external ram.

6-4 GENERAL REGISTER FILE (ON-BOARD RAM BANKS)
The 8065's on-board general register file is a keep-alive 491-word read/write static random
access memory (RAM) that is memory-mapped between addresses ^0024 thru ^03FF. To retain
the basic operand addressing scheme intrinsic to the instruction set common to all EEC-IV micro
processors, the general register file is divided into four RAM banks (RAM banks #0 thru #3).

What is the significance of a "single bank" 8065? I thought they are all capable of memory expansion, which would be easy enough to test on the P3M with a test program and a multimeter, and this should have nothing to do with register "RAM bank" access.

In researching the hardware reference manual I made some observations, some of which have been covered before:
"Mask Options" are for external memories and refer to address masks.

A "Step" is also referred to as a "design level" as in " [...]the 8061 40-pin silicon design level step "D" Indicates the status of the[...]" "[...]This restriction is applicable to all 8061 silicon prior to step "D" level"[/list]

The table of part numbers indicates that in 1989 part numbers for the 8065 were still "TBD" yet the design level was already set to "D". That may mean that for all practical purposes "from step 'D'" applies to all production 8065s and would only not apply to engineering samples.

Hypothesis:
Design level step "D" 8065's were defective and did not perform direct word RAM bank access as documented. This was corrected in a later design revision. This has nothing to do with the DUCE address mask option "D".

Are there any 8065's produced before the one in P3M that are known to do direct work RAM bank switching as documented?

As I look through the hardware manual it is clear that information about the 8065 was preliminary. Part numbers are TBD, there is no section documenting the design levels are there are for other chips, and there are notes referring to the future such as

NOTE EITHER ADDRESS RANGE MASK OPTION "E"
OR AN ALTERNATE BANKING SCHEME WILL BE
DEFINED FOR RAM

You guys have way more experience looking at bins and EECs than I do so I will gladly accept evidence you have to the contrary, but my suspicion is that this difference in behavior was unintentional and it might be more accurate to say that the silicon was wrong than the documentation is wrong (and yes I know documentation is still wrong in places).

[sailorbob]

Apart from the P3M, is any one aware of any other EEC with an 8065 and only one bank of ROM?

[jsa]

I feel like pointing out that the documentation says the registers are actually implemented as SRAM and refers to them as RAM banks, which is no doubt a source of confusion. And yes, it is crucial for this conversation to make a distinction between external and internal memories and not to confused the register file with external ram.

Yes that it the point I'm trying to get across. Location of the memory matters.

What is the significance of a "single bank" 8065? I thought they are all capable of memory expansion, which would be easy enough to test on the P3M with a test program and a multimeter,

I expect an external multi bank rom would need to be in place. In theory a QH could be the external multi bank ROM.
P3M does not do the things all 8065 are supposed to do, so memory expansion is not absolutely certain.

and this should have nothing to do with register "RAM bank" access.

That seems the best assessment of how it is expected to work.

The table of part numbers indicates that in 1989 part numbers for the 8065 were still "TBD" yet the design level was already set to "D". That may mean that for all practical purposes "from step 'D'" applies to all production 8065s and would only not apply to engineering samples.

Reinforces my view that P3M has a step D uP or maybe higher.

Hypothesis:
Design level step "D" 8065's were defective and did not perform direct word RAM bank access as documented. This was corrected in a later design revision. This has nothing to do with the DUCE address mask option "D".

Sure 8065-D could indeed be defective.
Does that mean later 8065 that do sfr15+100 instead of, word srf15 is word sfr14, are also faulty?
I think not, so I'm leaning toward preliminary errors in the manuals as the most likely case.

RAM/DUCE/CART mask D may just be a coincidence. Coincidentilly VILE's uP and RAM have matching suffix's.
Could just be a pattern.

Are there any 8065's produced before the one in P3M that are known to do direct work RAM bank switching as documented?

Good question.

You guys have way more experience looking at bins and EECs than I do so I will gladly accept evidence you have to the contrary, but my suspicion is that this difference in behavior was unintentional and it might be more accurate to say that the silicon was wrong than the documentation is wrong (and yes I know documentation is still wrong in places).

The issue is that disassembling to certain parts of the documentation gives incorrect results. So from that perspective the documents are brilliant to have but must be disregarded when silicon does something different.

[jsa]

Apart from the P3M, is any one aware of any other EEC with an 8065 and only one bank of ROM?

Indeed more test subjects needed.
Anyone know of any?

The PWB in P3M has component skip markers, so somethine else is built on that circuit board.

[tvrfan]

Ok..

8065 always has 0-0x3ff as INTERNAL ram (= registers) organised as 4 RAM banks, so that all those 8061 instructions still work for 8 bit addresses (or in other words 'kludge 1').

I have a few single ROM bank 8065 bins, which I believe are all Australian vehicles (probably because of emission/ODB ? regs or similar) 4TAB, 4DBG are single (ROM) bank 8065 bins. They do not set "mem_expand" bit (bit 4 of 0xa).

From what I have seen on multibank bins, some of them do an initialisation loop that confirms that the software does not see any difference internal/external RAM, as has a loop which writes from below 0x3ff and simply rolls through to over 0x400, so there is no apparent 'join' or change.

BUT - As far as I know ALL EXTERNAL RAM is mapped into Bank 1 for multibanks, so RAM DOES have a bank, and what really happens is that below 0x400 the memory controller is all internal (no ROM bank, RAM bank and 'odd word' tricks apply) and that at 0x400 and over, the CPU switches to external memory controller, which always adds in current ROM bank, so it actually goes from 0x3fe, 0x3ff, 0x10400, 0x10401. (call this 'kludge 2')

Similarly most of the specialist chips (e.g. DUCE ) are mapped into bank 1 as if they are RAM addresses. Most RAM is mapped at 0x(10)400 upwards, but some later bins (e.g. RZAS series) also have RAM at 0x1e000 upwards. Some bins have code in bank 1, some only have data.

Examples - If it helps any - I ended up programming SAD (disassembler) so that it always works as multibank, and it sets up 8061 bins as if they are completely in bank 8, which is where multibanks start, and any address above 0xff for 8061, or 0x3ff for 8065, is automatically mapped into the default databank (8 for single ROM bank, 1 for 8065 multibanks). This seems to work correctly.

Perhaps see the addressing modes in a different way as well, which might help -
for 8065 ...
TWO address modes -
1) CPU internal. 8 bit, + 2 bits of RAMBANK. May (or may not) have the 'odd address' on some or all of them (jsa).
2) CPU external. 16 bit + 4 bits of ROMBANK. Always adds ROMBANK to address. (yes, only 2 bits used in EEC, but CPU has 4 bits)

(8061 is the same but without the banks, so 8 bit and 16 bit only)

Direct mode = (R30 = R32) All operands are CPU internal addresses.
Immediate mode = (R30 = value) Ra (first) operand is Internal, Rb is a plain value.
Indirect mode = (R30 = [R32]) Ra is internal, Rb is internal, but Rb value (16 bit) and ROMBANK is then fed as a 20 bit address to the EXTERNAL controller.
Indexed mode (R30 = [R32+x]) Ra is internal, Rb is internal, but Rb value+x (16 bit) and ROMBANK is then fed as a 20 bit address to the EXTERNAL controller.

So this view makes it easy to sort addresses by opcode address mode............other opcodes only ever work with cpu internal addresses (e.g. shifts/divide/multiply), and JUMP/CALLs can be taken as a type of indexed mode address (here+jump_offset+ROMBANK)

I hope that helps with stuff - it's actually logically totally consistent.

I've seen a few of these kind of 'kludges' in my time for ways to expand a 16 bit CPU to give it more memory. I worked on a 16 bit CPU which had 18 bit addresses and later version had 24 bit addressing, that CPU did its expanded memory addressing in a completely different way... (I could explain, but won't here unless someone asks)

[sailorbob]

I have a few single ROM bank 8065 bins, which I believe are all Australian vehicles (probably because of emission/ODB ? regs or similar) 4TAB, 4DBG are single (ROM) bank 8065 bins.

The ETV-557, and similar ETV-554 & ETV-556, hardware ECU's are 2 ROM bank 88k units.

BUT - As far as I know ALL EXTERNAL RAM is mapped into Bank 1 for multibanks, so RAM DOES have a bank,

External RAM can be configured as banks but I have never seen it done so. The hardware manual shows multiple external RAM banks when 16 ROM banks are being used with a 4 to 16 line decoder to give the 1 MB size and, as ollapa said above, mask option E or an alternative banking scheme is required. In terms of addressing the external RAM then I think we agreed previously that it was bank 1.

[jsa]

The ETV-557, and similar ETV-554 & ETV-556, hardware ECU's are 2 ROM bank 88k units.

Looking at 4DBG.bin which is a ETV-557 box, the 32kb bank does not appear to be active and can't find a B4_RA being enabled.

[sailorbob]

These are two banks ECU's even if the 32k bank is not used for program or calibration data. The 32k bank is used for the Ford copyright notice, strategy name and calibration ID etc.

From your previous posts, I thought the P3M ECU had only a single ROM bank; are you saying it has two ROM banks but only one of them is used?

[tvrfan]

...
In terms of addressing the external RAM then I think we agreed previously that it was bank 1.
...

Yeah, I was just covering my ass in case we find some really weird bin. I don't think we will, but the 'short ROM bank' + extra RAM (RZAS) was a surprise to me, so I'm keeping an open mind on everything. I have this odd memory of seeing a bin where one of the specialist chips was mapped into bank 0, but it could have been one of the consoles? ...or my brain....

Yes, CPU can do more than it is used for (e.g. 16 banks of 64K) and the CPU itself doesn't care what/where RAM and ROM and specialist chips are, it just sees addresses (the two types example above was to try to explain in a simple way, and it doesn't quite cover all possibilities). So the EEC maps used are a Ford design limitation and not a CPU one.

Most of the multi bank bins have copyright and calibration ref (?) text at end of highest bank, and I have seen a totally empty bank 9 with only that text in it, so 4DBG etc originals may have that too. It's not in my copy of the bin (no big deal). The 'empty' bank still had a loopback jump at 0x2000 and all its interrupt pointers set up.

[jsa]

These are two banks ECU's even if the 32k bank is not used for program or calibration data. The 32k bank is used for the Ford copyright notice, strategy name and calibration ID etc.

Yes, see that. Used but inactive.

From your previous posts, I thought the P3M ECU had only a single ROM bank.

Yes, 56kb.

[tvrfan]

What I said above about 'open minded' and bugs - just discovered my 4DBG bin copy *does* have a copyright and strategy text, but NOT in a proper bank structure (i.e. a start with interrupt pointers and a loopback jump. So that's something that I will have to get SAD to cater for.