Why auto disassembly is tough

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jsa
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Re: To carry or borrow ... Opinions ?

Post by jsa » Fri Mar 09, 2018 6:04 pm

tvrfan wrote:
Fri Mar 09, 2018 2:47 pm

so for JC/JNC
1. search back to last PSW setter opcode (or should this be a specific CARRY flag setter/clearer ? Hmmm...)
Yeah, both set and clear are equally important.

2. .... (too hard right now to handle subrs with return value !)
That would need tracking of the subr and its carry result so that it could be recognised at the caller level.
beware the rabit hole, LOL.
3. if search finds a CMP or a SUB (any others?) then use the 'borrow'
For what it's (not) worth I have only read about CMP & SUB as being >=.

Looked at divide in the handbook, evidently carry is not affected.
4. If search finds ADD (etc) then use 'carry'
No carry for multiply either, apparently.

5. If shift, then use shift out (top or bottom, I guess SHL could be 'if (B4_R32 = 1) style, but probably never used that way
That style would make sense where followed by a jump.
From memory, I thought CARD had at least one example of that...somewhere...
Last edited by jsa on Sat Mar 10, 2018 7:59 am, edited 1 time in total.
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Re: To carry or borrow ... Opinions ?

Post by sailorbob » Sat Mar 10, 2018 5:14 am

I was expecting a comment about my order of the operands :smile:

Section C of the eec-iv pocket reference guide gives the operation of the instruction and the object code format, not the assembly language format. I prefer to see and use assembly code in the style of the Intel macro assemblers for their 8xxx processors (obviously disassembly listings give specific mnemonics for instructions rather than the generic mnemonics you can utilise to cover several instructions when using an assembler ).

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Re: Why auto disassembly is tough

Post by jsa » Sat Mar 10, 2018 7:58 am

What.........
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Re: Why auto disassembly is tough

Post by sailorbob » Sat Mar 10, 2018 9:56 am

Using the AD3W instruction as an example you get the following for adding the values from R34 and R36 and storing the result in R32:

Code: Select all

; Object code:
;
44363432
Not very easy to understand which is why we use higher level languages :smile:

Code: Select all

; Disassembly listing:
;
44363432	ad3w  	r32, r34, r36
Note that in this disassembly the object code has been included in the line and it can be seen that the operands are in reverse order to that of the object code.

Code: Select all

; Assembly code:
;
add word	r32, r34, r36
The assembler does not need to know it's a 'add 3 words' or a 'add 2 words' instruction as it works that out from the the number of operands.

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Re: Why auto disassembly is tough

Post by tvrfan » Sat Mar 10, 2018 3:31 pm

I'll add my 2c worth in case it helps any
for SAD disassembler, I do often 'swop' the conditional logic over to produce a 'C' like setup with brackets

CMP R32, R34;
JNE 12345; if (R34 = R32) {
.... }

which 'reverses' the jump (i.e. only enters brackets if jump is NOT taken)
So this can add confusion - when I'm debugging I typically go back to the actual opcode to check...
I was unhappy with carry as it didn't look right, but left it to fix other stuff.

Format - I copied the 8096 format, which Ford also use in their handbook.
For an easy rule of thumb for reading , I treat the operands as BACKWARDS, like this - - -

AD3W, R32, R34, R36 is R36 = R34 + R32
AD3W, op1, op2, op3 is op3 = op2 + op1

This is also useful to remember that only the FIRST operand in the opcode (= last one in pseudo source) can be indexed or indirect or immediate - R32 position in the above example. I think this is always right, but may be an exception in there (I think of STW as an LDW with ops swopped).
In the same way, the WRITE operand (the one that gets written to) is always the same as the number of operands, or none, except for STW and STB.

You do have to be careful with CMP and SUB, which according to Ford handbook and 8096 is op3 or op2 = op2 - op1. This means that op1 > op2 will CLEAR carry, because it's using the BORROW setup. So therefore

Code: Select all

SUB R32, R34                      R34 = R34 - R32;
JLT  12345                          if (R32 > R34) goto 12345;     or....    if (R34 < 0) goto 12345;
JNC 12345                         if (unsigned) (R32 > R34) goto 12345;    as  JNC doesn't check the NEG flag, but JLT does.. 
That's my understanding , and I admit I didn't check operand order in the carry question !


Shift-wise, I can see JC/JNC being useful for a LEFT shift, as it signifies an overflow in the shift, but I can't honestly see any use for a JC/JNC after a right shift, because it doesn't really mean anything useful. If however, 8061 didn't have a JB/JNB (like the 8096 !) then it can be used to do the equivalent bit check logic.

And yes, I agree with Bob in that the actual arithmetic engine itself doesn't care about 2 or 3 operands, it still does same operation, just changes where result gets stored. And also same for CMP which is a SUB with no result store.

Sticky ? I can see why this is provided, but not seen it used in EEC stuff - that makes sense to me, as the whole point is to reduce complex calcs and replace with approximated lookup functions/tables instead ... so sticky bit is redundant.

And lastly a programmers note about nested if-thens etc, which I haven't got to work in SAD (yet)

if (conditiona) {
if (conditionb) {
<code> } }

is of course if (conditiona AND conditionb) but its reverse is if (! conditiona OR ! conditionb) where ! means NOT, as in C code

and if (condition) { } else { } actually looks like this in code (addresses are just an example )

3000 CMP A, B
3002 JNE 3018
3004 ... # if {...}

3016 JMP 3040
3018 ... # else {...}

3040....

where goto is last operand of the 'if' block, so it jumps over the 'else' , and the original if jumps to the 'else'
But when they get mixed up with loops and others gets a bit tricky to sort out.....


Please correct me if you find an error in here ! Thanks.
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Re: Why auto disassembly is tough

Post by tvrfan » Sun Mar 11, 2018 11:37 pm

quick update - I'm having a total nightmare with getting the signed and unsigned subr names right....one of those things that looks quite simple, but
across the various binaries it shows up the holes in my logic. The original setup didn't always work either.

I might go back to a 'data scan' method (looking for sign bit changes...).
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Re: Why auto disassembly is tough

Post by sailorbob » Tue Mar 13, 2018 3:42 am

tvrfan wrote:
Sat Mar 10, 2018 3:31 pm
Format - I copied the 8096 format, which Ford also use in their handbook.
For an easy rule of thumb for reading , I treat the operands as BACKWARDS, like this - - -

AD3W, R32, R34, R36 is R36 = R34 + R32
AD3W, op1, op2, op3 is op3 = op2 + op1
In the Intel documentation I have seen this is not their assembly language instruction format, it is:

Mnem Dest, Src1, Src2.

See table 2.6 of the Intel document 'Using the 8096' for examples of one, two and three operands with different addressing modes.

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Re: Why auto disassembly is tough

Post by tvrfan » Wed Mar 28, 2018 7:14 pm

Oops, Yes, you are right. I'm not sure where I remembered that from !! Probably crossed over from something else ...
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SAD Version 3.05 posted to Github

Post by tvrfan » Mon Apr 09, 2018 3:37 pm

I have fixed a few things, added back the command to specify 'special lookup' subroutines, reworked CARRY (again),
fixed a couple of other bugs I found when testing.

There's probably still more bugs to find, but I ran this on all my collection of bins.
Apart from known issues (like subroutine arguments) I think I fixed what was reported so far.
Autonames sort of work....


I've been wondering if should type up a 'SAD for non IT people' guide, with some basics on how binary/hex numbers work, some basics of CPU core, and assembler code basics and then explaining what the 1D and 2D lookups do, interrupts and so on...

Would this help anyone here ??

(No I'm NOT going to call it an "Idiot's Guide" somehow I always thought that was demeaning "Total Newbie" would be better....)
Last edited by tvrfan on Mon Apr 09, 2018 4:57 pm, edited 1 time in total.
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Re: Why auto disassembly is tough

Post by cgrey8 » Mon Apr 09, 2018 4:03 pm

I know a primer like that couldn't hurt. As I mentioned in my PM to you (and others), I'll need something like this to concoct up simple machine code to do data-marshalling between the EEC and MBus. Today, I bought the hardware I'll need to get an EEC's J3 MBus pins connected to a Beaglebone.

Edit:
I split the posts related to the EEC Primer document out into it's own thread. Here's the link:
EEC Primer Doc
...Always Somethin'

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Re: SAD Version 3.05 posted to Github

Post by jsa » Tue Apr 10, 2018 3:53 am

tvrfan wrote:
Mon Apr 09, 2018 3:37 pm
reworked CARRY (again),
Thanks again for the hard work.

I'm liking the comments, to make obvious what goes with carries that are the result of ad2w and the like.

Some CARD

Code: Select all

6f2b: a4,56,52            adcw  R52,R56          R52 += R56 + CY;
6f2e: 37,57,0f            jnb   B7,R57,6f40      if (B7_R57 = 0) goto 6f40;
6f31: db,0f               jc    6f42             if (CY = 1) goto 6f42;            ## jump if (R52+R56) > 0xffff 
How about, ## jump if (R52+R56+CY) > 0xffff
Cheers

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Re: Why auto disassembly is tough

Post by tvrfan » Tue Apr 10, 2018 6:45 pm

What you're not going to give me even a day before reporting a new bug ??? AAARRRGHHHH !!!!!

Seriously but - you are right, I didn't spot that when checking. It does indeed need to have the CY flag added/subtracted for those opcodes.

So this is Bug 1 already.

I added a comment for JC/JNC because there's no arithmetically correct way to follow say, an AD2W with an if ...

i.e.

R36 = R36 + R34

if ((R36 + R34) > 0xffff) ... but it's already been added to R36 - does this mean do it again ?
if (R36 > 0xffff) .. but it CANNOT physically be on a 16 bit machine

And it means now I have a mechanism to put 'auto comments' in the code, which wasn't there before....

NB. I'm still not sure the naming works right, but at least you can now specify the lookup subroutines and names manually.
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Re: Why auto disassembly is tough

Post by jsa » Tue Apr 10, 2018 7:34 pm

tvrfan wrote:
Tue Apr 10, 2018 6:45 pm
What you're not going to give me even a day before reporting a new bug ??? AAARRRGHHHH !!!!!
:lol: :twisted: :lol:

I didn't want you thinking you went to a whole pile of effort and no one looked or even cares!

It will be the weekend before I get to look in more detail. That one just jumped out at me as I was looking at the new stuff you mentioned.

R36 = R36 + R34

if ((R36 + R34) > 0xffff) ... but it's already been added to R36 - does this mean do it again ?
I could see that misleading the uninitiated, defeating the point of having this heads up info.
if (R36 > 0xffff) .. but it CANNOT physically be on a 16 bit machine
True and that is the point of it, goto something else once reaching 2^16 and the carry is set.
Makes sense to me at least.

And it means now I have a mechanism to put 'auto comments' in the code, which wasn't there before....
Yes, I like that. How about adding bits affected by ands and ors'.
NB. I'm still not sure the naming works right, but at least you can now specify the lookup subroutines and names manually.
Cool, I will get some time on the weekend.
Cheers

John

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Re: Why auto disassembly is tough

Post by tvrfan » Tue Apr 10, 2018 9:20 pm

jsa wrote:
Tue Apr 10, 2018 7:34 pm
... Yes, I like that. How about adding bits affected by ands and ors'.
Unless I am misunderstanding, if you add a symbol name for a single bit SYM 1234 "flagx" : T 5 (would be bit 5)
then ANDs and ORs which are immediates (i.e. fixed values) should already be converted to 'flagx = 0;' or 'flagx = 1;'
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Re: Why auto disassembly is tough

Post by motorhead1991 » Thu Apr 12, 2018 11:11 am

I need to sync the current SAD source up with the OpenEEC code. I've been lostin Android land again and haven't done it 😁
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Re: Why auto disassembly is tough

Post by jsa » Fri Apr 13, 2018 12:22 am

tvrfan wrote:
Tue Apr 10, 2018 9:20 pm

Unless I am misunderstanding, if you add a symbol name for a single bit SYM 1234 "flagx" : T 5 (would be bit 5)
then ANDs and ORs which are immediates (i.e. fixed values) should already be converted to 'flagx = 0;' or 'flagx = 1;'
You might just have me nailed there, it is something I have not done yet.
How would that work out with scratch registers?

I have this in my comments;

Code: Select all

2082: 91,10,24          orb   R24,10         R24 |= 10;                     # B4 Set 1

216e: 71,fe,eb          an2b  Reb,fe         Reb &= fe;                     # B0 Clear 0
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Re: Why auto disassembly is tough

Post by jsa » Fri Apr 13, 2018 2:00 am

tvrfan wrote:
Tue Apr 10, 2018 6:45 pm

I added a comment for JC/JNC because there's no arithmetically correct way to follow say, an AD2W with an if ...
How about comments for Inc and Dec

Code from A9L. Some similar in CARD

Code: Select all

3cd8: 17,34               incb  R34              R34++;
3cda: d3,02               jnc   3cde             if (CY = 1)  {
Being addition I think carry is set once R34 exceeds 0xff
if (R34 > 0xff) {


CARD Code

Code: Select all

bc13: 05,34               decw  R34              R34--;
bc15: db,02               jc    bc19             if (CY = 0)  {
I am sitting on the fence with that one.
It is subtraction, but the 8096 Doc is silent on the carry being the complement for DECx, however the Doc is explicit for compare and subtract. Thoughts ?
Cheers

John

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Re: Why auto disassembly is tough

Post by jsa » Fri Apr 13, 2018 7:36 pm

jsa wrote:
Thu Feb 22, 2018 11:35 pm

I have this
vect 2DAC 2E0D : N
in V0.5 dir to get the Sub names beside the vector list. V3 is happy without it.
I see it is, no longer legal in 3.05. I like the new error checking output to msg, very good.

Code: Select all

vect 2DAC 2E0D :N 

                ^ Illegal Option
Cheers

John

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Re: Why auto disassembly is tough

Post by tvrfan » Fri Apr 13, 2018 7:37 pm

Thanks jsa - you spot the details I miss !!

I can honestly say I completely missed INC and DEC as possibly being used with carry ... DUH ! Stupid error.

Flag/bit names - again another slight catch 22 here - and an idea...

For scratch registers (typically R30 - R40 seem to be used a lot), sometimes it's several flags at once,
and sometimes its a genuine number mask (like for example A/D reads are only 10 bits). So where the AND and OR is done
with an immediate value, SAD looks for any bit names.
I was wondering whether to have a TYPE of variable as 'FLAGS' to define this behaviour, but it still wouldn't work for scratch/temp registers.

BUT also have in the background the idea that you can declare data types and they would be tracked/transferable.....
- i.e Types
Plain Word, Byte, Flags (word,byte) Nothing. perhaps signed/unsigned ?

IOtime (word/byte. long?) autoconvert to millisecs, but would require clock speed, unless I can spot a way to get it from code. (Timers subroutine?)
ADvalue (word), auto convert to volts 0-5
RPM (word) auto convert (divide by 4) all are x4 as far as I can see. seems to be a standard
Temp ? trickier, as Euro tend to use C and US ones use F (well, A9L does, don't know if later ones went metric)

After that so far I see other variables don't have a common calibration, but perhaps could declare them .
or perhaps allow the idea of a divisor/multiplier factor on all SYM (only on tables/funcs to 3.05) which get used in print phase ?

The the idea that when you do R34 = R36, or R34 = [1234] the TYPE (or divisor) of the variable gets transferred to R34 as well as its value.

But then I can't decide if it's too complex....what if two different types get added ?

Anyway I need to sort out in-line subroutine arguments first.... But ideas welcome, if I can do it (relatively) easily.

here's a section of AA code to show flag names, HSI sample has no named flags

Code: Select all

2174: 3a,5a,05            jb    B2,R5a,217c      if (PUMP_Reqd = 0)  {
2177: 71,7f,02            an2b  R2,7f            FPUMP_DRV = 0;
217a: 20,03               sjmp  217f             goto 217f; }
217c: 91,80,02            orb   R2,80            FPUMP_DRV = 1;
217f: 71,ef,5a            an2b  R5a,ef           STI_Reqd = 0;
2182: 3b,0b,03            jb    B3,Rb,2188       if (B3_HSI_Sample = 0)  {
2185: 91,10,5a            orb   R5a,10           STI_Reqd = 1; }
2188: 71,df,b7            an2b  Rb7,df           Idle_Adjust = 0;
218b: 3d,0b,03            jb    B5,Rb,2191       if (B5_HSI_Sample = 0)  {
218e: 91,20,b7            orb   Rb7,20           Idle_Adjust = 1; }
2191: ef,f6,09            call  2b8a             STO_OUT();
with these in _dir file

SYM 5a "PUMP_Reqd" : T +2
SYM 5a "STO_Reqd" : T +3
SYM 5a "STI_Reqd" : T +4
SYM 5a "TRIP_Reqd" : T +5
SYM 5a "ISC_Calc_reqd" : T +6
SYM 5a "ISC_Tmr_reqd" : T +7

etc....
-
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Re: Why auto disassembly is tough

Post by tvrfan » Fri Apr 13, 2018 7:42 pm

jsa wrote:
Fri Apr 13, 2018 7:36 pm
jsa wrote:
Thu Feb 22, 2018 11:35 pm

I have this
vect 2DAC 2E0D : N
in V0.5 dir to get the Sub names beside the vector list. V3 is happy without it.
I see it is, no longer legal in 3.05. I like the new error checking output to msg, very good.

Code: Select all

vect 2DAC 2E0D :N 

                ^ Illegal Option
I fixed a bug for multibanks (vect can point to a different bank), and realised the N is redundant (names added automatically)
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Re: Why auto disassembly is tough

Post by jsa » Fri Apr 13, 2018 9:15 pm

Thanks for confirmation on VECT.

I'll ponder your post, 2 up, a little before replying to it.

I have copied the arguments for this from a raw MSG file to a DIR and named it how I like.

Code: Select all

sub 7773 "Sub7773"   : E 4 f0 N : Y O 2 :Prenc L1=1* L2=0 P=4 D=32 A=87773 :FnLU L1=0 L2=0 P=0 D=0 A=87794 : F 1 32 Y S S
After running SAD the with the DIR the directive is ignored and an error is output to the new MSG.

Code: Select all

sub 7773 "Sub7773"   : E 4 f0 N : Y O 2 :Prenc L1=1* L2=0 P=4 D=32 A=87773 :FnLU L1=0 L2=0 P=0 D=0 A=87794 : F 1 32 Y S S

                                          ^ Param reqd
EDIT 1: Deleted Prenc argument, and Y O 2 had to become W N for naming of the function and argument. However, a hanging comma remains

Code: Select all

2375: ef,fb,53            call  7773             Sub7773(F.FN_Name,SYM_Name,);
Cheers

John

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Re: Why auto disassembly is tough

Post by tvrfan » Sat Apr 14, 2018 12:09 am

3.06 - waiting for any more bugs to be found before I release it.

Fixed the 'add and Carry' comment for JC/JNC not including the CY flag
Removed incorrect debug info in subroutine listings (which caused the Prenc and comma problem)
Added comment for JC/JNC after INC or DEC opcodes.

Thanks John
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Re: Why auto disassembly is tough

Post by motorhead1991 » Sat Apr 14, 2018 12:19 am

So uh, I did a thing.... Testing it here in a second

The image is blurry AF, stupid Linux. Anyways, tvrfan your code is so good it's portable to Android.

Image
sad_1.png
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Last edited by motorhead1991 on Sat Apr 14, 2018 2:37 am, edited 2 times in total.
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Re: Why auto disassembly is tough

Post by jsa » Sat Apr 14, 2018 12:27 am

tvrfan wrote:
Sat Apr 14, 2018 12:09 am
3.06 - waiting for any more bugs to be found before I release it.
Cool, will let you know.
Cheers

John

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Re: Why auto disassembly is tough

Post by jsa » Sat Apr 14, 2018 3:45 am

Code: Select all

WORD C1C4 C1C5 "Calibration_Pntr_2_Rbase_0xF4"
Will give Illegal operation in the MSG and fail to show in LST

SYM "Calibration_Pntr_2_Rbase_0xF4" works
Cheers

John

95 Escort RS Cosworth - GHAJ0 / ANTI on a COSY box code
Moates QH & BE
ForDiag

jsa
Tuning Addict
Posts: 481
Joined: Sat Nov 23, 2013 7:28 pm
Location: 'straya

Re: Why auto disassembly is tough

Post by jsa » Sat Apr 14, 2018 4:25 am

Raw LST

Code: Select all

c8d6: ff,7f,d1,02   func         32767,  721
c8da: 50,00,d1,02   func            80,  721
c8de: 32,00,ae,07   func            50, 1966
c8e2: 0a,00,7b,14   func            10, 5243
c8e6: f6,ff,c3,35   func           -10,13763
c8ea: ec,ff,8f,42   func           -20,17039
c8ee: 00,80,8f,42   func        -32768,17039
c8f2: 00,80,8f,42   func        -32768,17039
c8f6: 00,80,8f,42   func        -32768,17039
c8fa: 00,80,8f,42   func        -32768,17039
c8fe: 00,80,8f,42   func        -32768,17039
Add divisors to DIR

Code: Select all

func C8D6 C901 :S W V +256 :W V +65536 P +5
Processed LST

Code: Select all

c8d6: ff,7f,d1,02   func           128   ,    0.01
c8da: 50,00,d1,02   func             0.31,    0.01
c8de: 32,00,ae,07   func             0.2 ,    0.03
c8e2: 0a,00,7b,14   func             0.04,    0.08
c8e6: f6,ff,c3,35   func            -0.04,    0.21
c8ea: ec,ff,8f,42   func            -0.08,    0.26
c8ee: 00,80,8f,42   func          -128   ,    0.26
c8f2: 00,80,8f,42   func          -128   ,    0.26
c8f6: 00,80,8f,42   func          -128   ,    0.26
c8fa: 00,80,8f,42   func          -128   ,    0.26
c8fe: 00,80,8f,42   func          -128   ,    0.26
Note max of 128

Additionally, more than 2 decimal places would be handy for Divisor in the DIR.
Cheers

John

95 Escort RS Cosworth - GHAJ0 / ANTI on a COSY box code
Moates QH & BE
ForDiag

jsa
Tuning Addict
Posts: 481
Joined: Sat Nov 23, 2013 7:28 pm
Location: 'straya

Re: Why auto disassembly is tough

Post by jsa » Sat Apr 14, 2018 6:22 am

In CARD SAD misses code from 0x4510 to 0x459E.
The dog chasing its tail seems to be R34 = 4510 and push(R34)

Code: Select all

4502: a1,10,45,34         ldw   R34,4510         R34 = 4510;
4506: 26,8c               sjmp  4394             goto 4394;

  Sub4508:
4508: 3d,e0,02            jb    B5,Re0,450d      if (B5_Re0 = 0)  {
450b: 29,1c               scall 4629             Sub4629(); }
450d: c8,34               push  R34              push(R34);
450f: f0                  ret                    return;

4510: 9b,70,99,00         cmpb  R0,[R70+99]      
Cheers

John

95 Escort RS Cosworth - GHAJ0 / ANTI on a COSY box code
Moates QH & BE
ForDiag

tvrfan
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Posts: 342
Joined: Sat May 14, 2011 11:41 pm
Location: New Zealand

Re: Why auto disassembly is tough

Post by tvrfan » Sat Apr 14, 2018 3:34 pm

motorhead1991 wrote:
Sat Apr 14, 2018 12:19 am
So uh, I did a thing.... Testing it here in a second
The image is blurry AF, stupid Linux. Anyways, tvrfan your code is so good it's portable to Android.
Well, from what techie stuff I read, Android is supposed to have a Linux kernel/core !
I am trying to keep the code 'clean' C/C++, so a certified compiler should make it runnable on any environment which has the standard 'C' libraries.
Code does expect at least a 32 bit compiler and environment.
As per Github, I use exactly the same code for Win32 and Linux 64.

Good to know though ..... see the advert .....!!! SAD NOW RUNS ON MOBILE DEVICES !!!
TVR, Triumph (cars), kit cars, classics. Ex IT geek, development and databases.

https://github.com/tvrfan/EEC-IV-disassembler

tvrfan
Tuning Addict
Posts: 342
Joined: Sat May 14, 2011 11:41 pm
Location: New Zealand

Re: Why auto disassembly is tough

Post by tvrfan » Sat Apr 14, 2018 3:41 pm

jsa wrote:
Sat Apr 14, 2018 6:22 am
In CARD SAD misses code from 0x4510 to 0x459E.
The dog chasing its tail seems to be R34 = 4510 and push(R34)
Happens in A9L as well.

This is down to the way SAD chops up the code into 'blocks' and then links them with a tree structure.
It sees no link between the load and the push/ret.
When I put code in to handle this, it also produces lots of invalid address hits, which often messes up the disassembly.
I haven't solved it yet...

if the code had PUSH, 4510 then that works correctly.

For now, a SCAN 4510 should give a work around ...
TVR, Triumph (cars), kit cars, classics. Ex IT geek, development and databases.

https://github.com/tvrfan/EEC-IV-disassembler

jsa
Tuning Addict
Posts: 481
Joined: Sat Nov 23, 2013 7:28 pm
Location: 'straya

Re: Why auto disassembly is tough

Post by jsa » Sat Apr 14, 2018 4:07 pm

Output to MSG file.

Code: Select all

timel   ba73 bba6: W N 
Does it need a space before the colon, I have not tested it.
Cheers

John

95 Escort RS Cosworth - GHAJ0 / ANTI on a COSY box code
Moates QH & BE
ForDiag

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