Why auto disassembly is tough

This is where the BIN Hackers and definition junkies discuss the inner workings of the EEC code and hardware. General tuning questions do not go here. Only technical/hardware-specific/code questions and discussions belong here.

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cgrey8
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Re: Why auto disassembly is tough

Post by cgrey8 » Wed Jun 12, 2019 6:58 am

This may be a stupid question, but in that code snippet, I see that interrupts get disabled right before entering the critical section of the sub where stack manipulation is done. But I don't see an explicit re-enabling of the interrupts.
Is that done implicitly by one of the other ops?
Or is it simply part of this sub's job to disable interrupts and return with them still disabled?
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sailorbob
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Re: Why auto disassembly is tough

Post by sailorbob » Wed Jun 12, 2019 8:31 am

The interrupts are not necessarily enabled after the subroutine has finished being executed. The PUSHP instruction saves the PSW register to the stack and bit 15 is the 'interrupt enable' bit. The later POPW instruction restores the PSW register to the condition it was at the point when it was saved to the stack. This means the interrupt enable bit will be set to whatever it was when the subroutine was called.

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Re: Why auto disassembly is tough

Post by cgrey8 » Wed Jun 12, 2019 11:11 am

Ahh, the enable/disable of interrupts is being "managed" implicitly by virtue of the restoration of PSW. That makes sense now that you say it. But due to my lack of familiarity with the PSW reg, it didn't even occur to me that the Enable/Disable bit lived there.

Thanks for the clarification.
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Re: Why auto disassembly is tough

Post by sailorbob » Wed Jun 12, 2019 11:56 am

Sorry, I meant POPP not POPW above (that's a different instruction!).

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Re: Why auto disassembly is tough

Post by tvrfan » Wed Jun 12, 2019 2:49 pm

Guys,

Just for completeness, it's worth a quick review of the PSW on 8065 CPUs and bank operation.

Whilst the 8065 PSW lower byte contains the various status flags for conditional jumps (zero, negative, etc), the upper byte contains current program bank (which I take to mean 'code bank'), the current RAM bank, and the interrupt enable flag in bit 15.
The 8061 ALSO has the interrupt enable bit in PSW bit 15, but no bank info.

A POPP will therefore restore a previous interrupt enable state from a PUSHP on *ALL* bins.
It doesn't seem to be used in single banks (at least I've not seen one) but it would still be valid.

A long time ago we had a thread on here about how the multibanks kept track of arguments across banks, and now we know for sure.

Also note that the LDB R11, 11 sets the 'data' bank (bottom 4 bits) and the stack bank (where the stack resides) in the top 4 bits.
I don't think the stack bank does anything for EEC-IV bins, on the basis that stack has always to be somewhere in RAM.
The 4 bits are provided would seem like it's for a generic setup where ALL memory is RAM, more like a desktop computer setup.
That would make sense.

The ONLY way to get at the 'code' bank is via the PSW, or set it with a BNK (0x10) prefix as part of a JUMP or CALL instruction.
R11 is readable, so code can get directly at the current 'data' bank.

Also worth noting is that the idea of LDW [STACK + n] is perfectly valid for 8061 too, (stack would be R10), but it looks like the compilers (or people coding) didn't think of it at that time. A9L subroutines which get arguments on behalf of a different subr (0x3695 and for example) would be neater without those extra POPW instructions ......

Hope that helps !!
TVR, kit cars, classic cars. Ex IT geek, development and databases.
https://github.com/tvrfan/EEC-IV-disassembler

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