Following on....
I don't know if that pseudo code came from SAD or not, I discovered this bug in SAD a while ago - what should happen is that the pseudo code generator should look for the last opcode which sets the PSW, and it wasn't, it was just doing last instruction. So be aware !!
R72 - In A9l near the beginning, it sets up its 'base' registers in a subroutine (Rf0 - Rfe) and it also sets some RAM/KAM ptrs too, for every background loop ...
Code: Select all
2162: a1,80,01,72 ldw R72,180
2166: a1,7e,02,74 ldw R74,27e
216a: a1,7a,03,76 ldw R76,37a
so that value you refer to will probably be a stored or 'learned' parameter.
In the description of the PSW in 8096/196 (and in the Ford eec book) there is a description of what those flags are....
this cut and pasted, so layout is all messed up, but here my best edit attempt.....
[and my note - As I remember a 'signed overflow' as with that A9L example above, one can't assume the V flag is set, but the 'N' flag will be set, so you check a greater or equals. Example
0x6000 + 0x6000 = 0xc000 this is a signed overflow as result goes negative. In decimal 24576+24576 = -49151 (I think that's right....) ]
Table A-2. Processor Status Word (PSW) Flags
Mnemonic Description
C The carry flag is set to indicate an arithmetic carry from the MSB of the ALU or the state of
the last bit shifted out of an operand. If a subtraction operation generates a borrow, the
carry flag is cleared.
C , Value of Bits Shifted Off
0 < 1⁄2 LSB
1 ≥ 1⁄2 LSB
Normally, the result is rounded up if the carry flag is set. The sticky bit flag allows a finer
resolution in the rounding decision.
C ST Value of Bits Shifted Off
0 0 = 0
0 1 > 0 and < 1⁄2 LSB
1 0 = 1⁄2 LSB
1 1 > 1⁄2 LSB and < 1 LSB
N The negative flag is set to indicate that an operation generated a negative result. It is
correct even if an overflow occurs. For all shift operations and the NORML instruction, the
flag is set or cleared to equal the most-significant bit of the result, even if the shift count is
zero.
ST The sticky bit flag is set to indicate that, during a right shift, a “1” has been shifted into the
carry flag and then shifted out. This bit is undefined after a multiply operation. The sticky
bit flag can be used with the carry flag to allow finer resolution in rounding decisions. See
the description of the carry (C) flag for details.
V The overflow flag is set to indicate that the result of an operation is too large to be
represented correctly in the available space.
For shift operations, the flag is set if the most-significant bit of the operand changes during
the shift.
For divide operations, the quotient is stored in the low-order half of the destination
operand and the remainder is stored in the high-order half. The overflow flag is set if the
quotient is outside the range for the low-order half of the destination operand. (Chapter 3,
“Programming ConsiderAtions,” defines the operands and possible values for each.)
Instruction Quotient Stored in:
V Flag Set if Quotient is:
DIVB Short-Integer DIV Integer
< –128 (81H) or > +127 (7FH)
< –32768 (8001H) or > +32767 (7FFFH)
DIVUB Byte > 255 (0FFH)
DIVU Word > 65535 (0FFFFH)
VT The overflow-trap flag is set when the overflow flag is set, but it is cleared only by the
CLRVT, JVT, and JNVT instructions. This allows testing for a possible overflow at the end
of a sequence of related arithmetic operations, which is generally more efficient than
testing the overflow flag after each operation.
Z The zero flag is set to indicate that the result of an operation was zero. For add-with-carry
and subtract-with-borrow operations, the flag is never set, but it is cleared if the result is
other than zero. Therefore, the zero flag indicates the correct zero or non-zero result for
multiple-precision calculations.