There's mention of it in the EEC Memory Control section:
Plus there's a diagram:The memory system’s efficiency comes from the fact that there are two
internal address registers in the ROM, and three internal address registers in the
But that's about all the information I can find about this register. The rest of the EEC Memory Control section only discusses the SPC and the DAR and I don't see how the existing MBUS control lines could signal a transfer of data in or out of a third register. Is it real? If so what is it used for and how is it accessed?