[ollopa]

Does anyone know anything about the EER described in eectch98?

There's mention of it in the EEC Memory Control section:

The memory system’s efficiency comes from the fact that there are two
internal address registers in the ROM, and three internal address registers in the
RAM.

Plus there's a diagram:

EEC EER.jpg (53.24 KiB) Viewed 9348 times

But that's about all the information I can find about this register. The rest of the EEC Memory Control section only discusses the SPC and the DAR and I don't see how the existing MBUS control lines could signal a transfer of data in or out of a third register. Is it real? If so what is it used for and how is it accessed?

[sailorbob]

The Execute Enable Register (aka EER) is a write only memory address within the ram (the address varies according to the RAM type). Its purpose is to enable or disable the reading of a MCU instruction from the RAM. A value of 0xAA is enable, any other value is disable and at power up it is initialised to a value of 0x00.

[ollopa]

So is it accessed via the DAR like other RAM contents?

It sounds like you're saying that normally if you use the RAM's SPC to read, it probably just floats the bus and you get 0xFF's unless the EER was written 0xAA.

Please confirm my ignorance or deny my understanding

[Tun3r]

Updates please

[ollopa]

81C6x Block Diagram.jpg (103.38 KiB) Viewed 6970 times

14-4.4 EXECUTE ENABLE REGISTER (EER)

The EER is a memory-mapped 8-bit data holding register that is used to enable and disable the
address outputs of the SPC. The SPC address outputs are used to address program instruction
locations in RAM. The outputs of the SPC are enabled when data pattern ^AA is written into the EER.
Any other data pattern written into the EER disables these outputs.

Data is written into the EER when the EER is addressed by the data address register and the device
is in the "Write RAM, I/O Port, and EER" mode of operation. [Note: There are two EER address mask
options (A and C) available for the 81C61 and 81C62. Device mask option "B" does not have an EER,
see "Address Mask Options" in this chapter.] Due to device architecture, data written into the EER
cannot be read. In the device standby mode or following a device power-up, the EER contents are set
to zero. For additional information on the EER, see "Functional Operation" in this chapter.

14-5.3 WRITING THE EXECUTE ENABLE REGISTER

The execute enable register (EER) is written with a unique pattern (^AA) to enable the slave
program counter (SPC) to address program instruction locations in RAM. Writing any other
pattern into the EER disables the SPC from addressing RAM. Before the EER can be written, it must
be accessed by the data address register (DAR). The address of the EER is loaded into the DAR in the
"Load Data Address Register" mode. Immediately thereafter, the EER must be written with data in
the "Write RAM, EER, or i/0 Ports" mode and is a device operational requirement. Writing data
into the EER occurs on the first STB puise after entering the "Write RAM, EER, or i/0 Ports" mode