[ollopa]

Information wants to be free... That was proven when we were blessed with the Custom IC Pocket Reference Guide. Now after years of sifting through the results of a daily saved search, the complete hardware architecture reference and EEC-IV software manuals emerged and I was able to acquire them. Total cost with tax and shipping was close to 300USD. The seller told me a family member was an engineer at Ford.

Books.jpg (107.06 KiB) Viewed 127342 times

I've only had these a few days and have just finished scanning and preparing 1,024 pages into high detail, high quality searchable PDFs which I am now making freely available to everyone HERE.

There's detailed information on all the custom chips in the EEC including programming of the EPROMs and EEPROM, peripheral registers, performing A/D conversions, PWM calculations for DUCE, etc. There's very detailed information on MBus operating and timing in case we want to make a new J3 device. There is a list of unassigned opcodes and how the CPU responds to them, which is novel trivia but also an indication of how much detail is provided.

Although the text is OCRd and searchable, the PDF bookmarks still had to be added by hand. I added fairly complete bookmarks following the table of contents but I didn't have the patience to bookmark every single section at all levels of hierarchy. I recommend browsing through the whole document at least once to gain familiarity instead of just clicking through my bookmarks.

I'll reiterate that I'm giving this away for free but if, however, anyone wishes to send me some beer money in appreciation, I certainly won't turn it away I'll leave this here just in case:

[sailorbob]

What a great find, thank you very much!

[jsa]

Wow, thank you, that is very much appreciated.

Great detective work, to track that down.

Absolutely worth some beers. :thumbup:

[tvrfan]

F-A-N-T-A-S-T-I-C !!!!!

I've scanned the'software' one and it contains EVERYTHING, including details about some of those nagging little questions we had about edge conditions, odd stuff found in bin code etc. Wonderful.

The handbook was brilliant, this is a step above that.

Great. I now don't have to ask Sailorbob about anything, and can probably prove him wrong on something

[ollopa]

:) Be sure to cruise through the custom IC reference as well. It covers a lot of the same topics but occasionally has a different insight or detail. Both are invaluable!

[tvrfan]

BUMP.

This deserves to be at the top for a while longer !!

[jsa]

Calibration console pic.
https://www.thehenryford.org/collection ... act/246550

[ollopa]

I've reached out to The Henry Ford / Benson Ford Research Center three times in the past couple of years to discuss gaining access to their calibration console manual. I just got a reply this morning that appears positive but there's a nontrivial fee to retrieve it from storage and make a copy of the manual. Stay tuned and hopefully in the next few weeks or months I'll have an update :)

[jsa]

Excellent!

Do them a deal on a couple manuals....

[Chucko]

Sweet! Thank you for sharing this.

[Chucko]

Now if only someone could find a schematic for the Fox MAF EEC. There's an EEC-IV schematic floating around the web but it's a bank fire, MAP EEC.

I'd LOVE to know what's in those hybrid modules.

[jsa]

I 2nd the interest in the hybrids.

Hyb 27 VS hyb 34, etc.

[ironmanisanemic]

Now if only someone could find a schematic for the Fox MAF EEC. There's an EEC-IV schematic floating around the web but it's a bank fire, MAP EEC.

I'd LOVE to know what's in those hybrid modules.

Would you by chance have a link to this schematic? ive been looking and have yet to find anything like that. I am currently trying to reverse engineer the hardware myself, and from what ive seen many of the circuits appear to be laid out similarly. Having a good jumping off point would be nice instead of having to reinvent the wheel.

From what i can gather so far, some of the hybrid modules seem to perform functions the same as other ICs, just with reduced funcionality or maybe just a different footprint to save space. A 2 bank SD ecu that i am starting with only has one HEGO input, but Ford used a dedicated IC for dual HEGO signal conditioning, but on this ecu, it uses a reduced pinout hybrid module to handle just the one HEGO input.

[ollopa]

I believe it's over here https://www.merkurencyclopedia.com/EEC- ... esign.html

Specifically

That page also has a very low res B&W scan of a page from the pocket reference. The alignment doesn't quite match the color photos of the same page of the reference, so I think it's a unique scan or fax. I wonder if that could be a lead to a person in possession of the pocket reference... Does anybody know Allan Slocum to ask where it came from?

[ironmanisanemic]

The pocket reference is in the link in my signature.

I believe it's over here https://www.merkurencyclopedia.com/EEC- ... esign.html

Specifically

That page also has a very low res B&W scan of a page from the pocket reference. The alignment doesn't quite match the color photos of the same page of the reference, so I think it's a unique scan or fax. I wonder if that could be a lead to a person in possession of the pocket reference... Does anybody know Allan Slocum to ask where it came from?

[ollopa]

I'm interested in who has the physical item, the story of where it came from, and what else they might be in possession of. Also a few pages of the pocket reference are rather blurry and it would be nice to re-photograph them or, better yet, remove the binding and scan them through a ScanSnap or similar quality document scanner.

[ollopa]

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Got it and added it to my Google drive (see link in first post).
I was hoping for more theory of operation and technical bits but it's basically an operator's manual. It does have examples of the DOC cards that calibration engineers would use to navigate a strategy, which I found interesting. The appendices are also interesting with the list of strategy terms and binary point conversion tables.

[jsa]

@ollopa

Thanks for the CC training manual.

Those doc files would make def creation much easier.

[motorhead1991]

calibrationconsole.jpg


Got it and added it to my Google drive (see link in first post).
I was hoping for more theory of operation and technical bits but it's basically an operator's manual. It does have examples of the DOC cards that calibration engineers would use to navigate a strategy, which I found interesting. The appendices are also interesting with the list of strategy terms and binary point conversion tables.

PM me your email address and I can credit you on Github so I can back these up.

[Veiveismart]

This is a very valuable deal

[jsa]

PYM, TVRFan and I have been picking the eyes out of these manuals, however it has become apparent that not all is exactly as described.

I have written test bins to dis/prove conjecture around the SF/R+100 memory offset.
The files can be found at;
https://github.com/OpenEEC-Project/EEC- ... -Test-Bins

[wwhite]

however it has become apparent that not all is exactly as described.

It is all exactly as described. If your EEC-IV/V doesn't have the memory to support multiple ROM/RAM banks, there will not be any bank memory offsets happening.
The uP supports it just fine, its the EECs with 64K only that do not.

It's all in the manuals.

[jsa]

We beat this to death on the other forum.

There are parts of the manuals that are at odds with the way it actually works in silicon.

So far all the 8065's have R0-R3FF internal to the uP, that is the area where +100 address mode operates.

[tvrfan]

however it has become apparent that not all is exactly as described.

It is all exactly as described. If your EEC-IV/V doesn't have the memory to support multiple ROM/RAM banks, there will not be any bank memory offsets happening.
The uP supports it just fine, its the EECs with 64K only that do not.

It's all in the manuals.

I will simply point out that the date of the manuals are Feb 1989 and May 1990 (page 3), and say 'EEC-IV' all over them. So no mention of EEC-V, and yet this CPU was used until, er.. 2005? So the manuals will be indeed be totally correct for any box made up to 1990.

After that it's likely that development has continued. Those manuals are still valid for vast majority of design, but small details have likely changed over time (which is what we are investigating). I don't think those manuals mention high address RAM in bank 1, for example, but we *know* and can prove that happened, we have the bins.

And anyway, having been in IT for many years, how often does a tech doc slip through with mistakes in it, even in final publication ? Been there.....

Have you ever seen an 8063 in any box ???

So it's not trying to say docs are wrong or anything, just that some minor design tweaks probably happened and are not in those manuals, so looking in the bin code makes you say "Uh...What?" . Which is where jsa is at....

[sailorbob]

The hardware reference manual states the 8063 was only used in development and wasn't put into production ECU's.

Can anyone point me to a specific example of where the accessing of the upper 3 ram banks is not as described in the reference manuals? Also, I have not seen anything in the various disassemblies I have done to indicate that any 8065 does not have all 4 ram banks regardless of whether in memory expansion mode or not so I'm curious if there is anything different in the silicon.

[tvrfan]

The hardware reference manual states the 8063 was only used in development and wasn't put into production ECU's.

Can anyone point me to a specific example of where the accessing of the upper 3 ram banks is not as described in the reference manuals? Also, I have not seen anything in the various disassemblies I have done to indicate that any 8065 does not have all 4 ram banks regardless of whether in memory expansion mode or not so I'm curious if there is anything different in the silicon.

Bob, I didn't see that about 8063. OK.
I too assume 4 RAM banks are always there, and in the CPU chip itself, independent of any other H/W, and it doesn't change with mem_expand on or off.

What kicked this off is about the later added (?) feature of accessing direct registers as words with odd addresses being used to change RAM banks, and whether or not this applies for special func registers (addresses < 0x20 ). The Ford handbook, but not the manuals, has a reference to "from Step D" implying this 'odd word' direct mode was added to 8065 sometime later, but manuals imply it's always true. Neither mention SFRs in this context, but the manuals DO have a reference elsewhere to what happens when using odd addresses with SFRs, implying bank swop is NOT true for SFRs. (To me, I think the confusion may be in the way it's worded, which is not clear). Jsa found a bin which uses 0x9, and in the code context it makes sense if it actually is 0x108.

This also leads to 0x0, 0x100, 0x200, 0x300 can also be regarded as 'special', so does 0x1 work as 0x100 ?? Not that anyone would bother I guess, but still..... I think jsa found a bin that does NOT work this way ?? I'm not sure, but this is why he was asking the question.

Until I hear otherwise, my opinion is that this 'odd word' direct mode is ALWAYS true for ALL register addresses. For disassembly if the version of 8065 can't do this 'odd word' mode, then it won't appear, so it's safe to assume it's always true for disassembly ....

As to whether 'odd mode' changes in mem-expand, I don't think anyone has even asked THAT question until now ! (but I would assume not)

Has anyone got examples of using odd addresses with word mode special func registers ?? I expect not, but it's still a valid question to ask.

Over to anyone with examples.................

[sailorbob]

As the only SFRs in ram banks 1, 2 and 3 are 'zero registers' at 0x0100, and 0x0200 and 0x0300 respectively there is no need for a program to use the direct address mode 8 bit odd address method to read or write word sized data.

If there were SFRs in ram banks 1, 2, or 3 other than the 'zero registers' I doubt they would be treated any differently than how the GFR's are accessed.

[jsa]

As the only SFRs in ram banks 1, 2 and 3 are 'zero registers' at 0x0100, and 0x0200 and 0x0300 respectively there is no need for a program to use the direct address mode 8 bit odd address method to read or write word sized data.

Yep, this is not about the zero registers.

[jsa]

Software Manual Clause 3-2.2

When the LSB of an operand address Is "0",
the even bank Is accessed;when It Is "1",the odd bank Is accessed. The seven MSBs of the operand
address are used to access the operand location In the bank. This applies only to Ra of the direct
address mode,Rb,and Rd which reference on-board word and double-word operand locations. For
further Information on 8065 operand addresses, see "RAM Banks" In Chapter Six.

What does that really say, says only Ra then babbles on about Rb and Rd to muddy the meaning.
Later on there are code examples that contradict only.

Software Manual Figure 3-3

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Well, no, it applies to Rb and Rd, it also applies to Immediate, Indirect, Auto Incr, Short Index and Long Index.
Oh, wait none of it works in the very first 8065 I'm aware of, in production some years after the manual went to print.

Software Manual Clause 6-3

The column headed with an asterisk(*) in Table 6-2 defines how a specific SFR is to be accessed:
byte (B), word(W),or either byte or word (E).
.
.
If address location '^0015 is word referenced, for example, the high byte of the MSG interrupt
pending register#2 is accessed along with its low byte at address location '^0014.

Stick that in your pipe and smoke it! Reconcile that with 0x15 is 0x115.

Software Manual Table 6-2

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SFR07, SFR0F, SFR11, SFR13, SFR15, SFR17, SFR19, SFR1D, SFR21 and SFR23, what's it to be?? SFR word access or SFR +100??

Software Manual

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TVRfan kindly pointed this out after I published the test bins. Neat, a table labelled as Direct with Immediate examples.
How many wrote this manual?? Chapter 3 forgot to speak to Chapter 6.
Note Operand B and D in the 3W operations...no mention in the text...ok one point to the manual!

Software Manual Table 6-3

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Bit A0, -, Don't Care,

but it matters because those address modes do have operand b & d sf/r+100.


So, we have an Odd SFR word access to reconcile with Odd Word Operand Ram Bank access.
We also have unclear description of relevance to Operands A, B and D.
Also, the handbook only mentions Direct Word.


To much contradiction or failure to write about the functionality. How to get to the bottom of how it really works in silicon...write test bins.
Test results... an 8065 that does not support the claim by the manuals, and an 8065 that supports all manner of SFR+100, any operand, any address mode but forget about odd word access to the actual SFR.

Are there in between cases...test away...post your results.

Yes, as I have noted to TVRfan, treat the manuals with great suspicion they were printed well before production silicon and revisions thereof.

[sailorbob]

SFR07, SFR0F, SFR11, SFR13, SFR15, SFR17, SFR19, SFR1D, SFR21 and SFR23, what's it to be?? SFR word access or SFR +100??

I am not sure what your question is here. If you are trying to access these odd addressed SFR's you just you a use a byte read or write (where writes are permitted).

Stick that in your pipe and smoke it! Reconcile that with 0x15 is 0x115.

I think this is referring to using a 16 bit address to read or write word sized data and not the direct address mode 8 bit odd address method to read or write word sized data