This is where the BIN Hackers and definition junkies discuss the inner workings of the EEC code and hardware. General tuning questions do not go here. Only technical/hardware-specific/code questions and discussions belong here.

Moderators: cgrey8, EDS50, Jon 94GT, 2Shaker

Post Reply
jsa
Tuning Addict
Posts: 1201
Joined: Sat Nov 23, 2013 7:28 pm
Location: 'straya

SFR+100 and R+100 8065 memory access

Post by jsa » Mon Apr 05, 2021 5:51 am

PYM, TVRFan and I aware that the disassemblers are not handling SFR+100 and R+100 memory offsets in all cases.

I have written test bins to dis/prove conjecture around the SF/R+100 memory offset.
The files can be found at;
https://github.com/OpenEEC-Project/EEC- ... -Test-Bins

They are well worth a look.

We'd be interested in your results if you decide to run them on your own hardware.
Cheers

John

95 Escort RS Cosworth - CARD QUIK COSY ANTI / GHAJ0
Moates QH & BE
ForDiag

Post Reply

Who is online

Users browsing this forum: No registered users and 2 guests