Thanks for the clarification on the terminology. I'm sure it was just me getting lost in the jargon. But now that we have it spelled out explicitly, I can follow along.
As for the other updates, ALL great info. It's also interesting to hear that some strats maintain a higher resolution timer value to get longer timer times. I wonder if some of that came about due to the addition of OBD-II communication? From what I understand the OBD-II CAN protocol isn't that fast. Although the CAN interface itself is quite fast. Bypassing the the OBD-II stack to talk directly to the processor over the OBD-II port yields some decent datalogging and throughput times. Is there any chance the com port is running through the HSO? Or is the interface to the CAN controller its own register in the 8065?
Next, does anybody have any documentation to how the EEC communicates spark advance to the TFI and EDISx modules? I know it's pulse-width output so I'm ASSUMING the control is through the HSO like it is all the other pulse-width outputs. However the "protocol" I think is different. Or is it? And in the newer EECs, the EDIS circuitry is built into the EEC itself. However is it literally just an EDISx module made onto the same circuit-board, thus identical control in code, or were there changes to how the commanded spark advance is communicated to on-board EDIS vs when the EEC is controlling an EDISx module? This may need to be broken out into its own thread. If it gets more involved than just a single answer, I'll split the topic off.
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Re: How are interrupts setup on Intel 806x microcontrollers?
...Always Somethin'
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Re: How are interrupts setup on Intel 806x microcontrollers?
Times - My old box only uses 16 bit times, but having studied the A9L a little, it uses 24 bit times in its 'software' queue and its local copy of IOTIME, and then has an extra bit of check logic when it reads/writes out to the hardware 16 bit system to keep it all straight. It could be ODB as you say, but remember it's also cycling its timers twice as quick, so that's a neat way of getting multi second times.
Whilst talking times by the way, ALL the boxes I have seen also have a TIMER routine which does 'long term' timers, in millisecs, eighths of sec and seconds. These are declared in a table and incremented from the 'master' IO timer accordingly. That is, the routine code does the checks for 'new millsec, new eighth' etc, and then increments all qualifying timers.
These timers drive things like the error/MIL code output, accelerator pump, lean cruise, overrun lean out, etc. , so there are plenty of other timed functions going on separately from just IO.
TFI - I don't know how EDIS works, but the TFI module simply triggers on the EEC's STO in preference to the PIP, so if the STO arrives first, it will spark then, but if there's no STO, it sparks on the PIP signal. This is arranged cleverly on the basis of rising and falling pulse edges, so it all works neatly. This is why the EEC calculates advance for the NEXT spark, and triggers the STO 'early' , in effect. (this is with a TFI distributor of course)
In my box, the 'base' mode simply triggers STO as soon as a PIP interrupt comes in, and as RPM crosses the 'advance' threshold, it swops modes and starts triggering STO early according to its advance calc and the timing of PIP signals (which also is the RPM calc). At higher RPM it changes calc modes again, but effectively does the same thing.
At least that's how I understand it works - happy to be corrected !!
Whilst talking times by the way, ALL the boxes I have seen also have a TIMER routine which does 'long term' timers, in millisecs, eighths of sec and seconds. These are declared in a table and incremented from the 'master' IO timer accordingly. That is, the routine code does the checks for 'new millsec, new eighth' etc, and then increments all qualifying timers.
These timers drive things like the error/MIL code output, accelerator pump, lean cruise, overrun lean out, etc. , so there are plenty of other timed functions going on separately from just IO.
TFI - I don't know how EDIS works, but the TFI module simply triggers on the EEC's STO in preference to the PIP, so if the STO arrives first, it will spark then, but if there's no STO, it sparks on the PIP signal. This is arranged cleverly on the basis of rising and falling pulse edges, so it all works neatly. This is why the EEC calculates advance for the NEXT spark, and triggers the STO 'early' , in effect. (this is with a TFI distributor of course)
In my box, the 'base' mode simply triggers STO as soon as a PIP interrupt comes in, and as RPM crosses the 'advance' threshold, it swops modes and starts triggering STO early according to its advance calc and the timing of PIP signals (which also is the RPM calc). At higher RPM it changes calc modes again, but effectively does the same thing.
At least that's how I understand it works - happy to be corrected !!
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- cgrey8
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Re: How are interrupts setup on Intel 806x microcontrollers?
What is STO?
...Always Somethin'
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Re: How are interrupts setup on Intel 806x microcontrollers?
Oh dear, I didn't even notice THAT cockup. Apologies.....cgrey8 wrote:What is STO?
STO = self test out, which isn't even the right one.
It *should* read SPOUT = Spark Out, throughout that post.
(and just in case, PIP = Profile Ignition Pickup)
It must be old age ..... (slinks off in embarrassment)
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Re: How are interrupts setup on Intel 806x microcontrollers?
Ok, that makes much more sense. But SPOUT is controlled by the HSO though isn't it? Or is it a "Low Speed Output"?
And since it is brought up...is the STO also on the HSO?
And since it is brought up...is the STO also on the HSO?
...Always Somethin'
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Re: How are interrupts setup on Intel 806x microcontrollers?
On my old box (from 1985 by the way), the only thing driven by the low speed output is the fuel pump relay. Everything else is done via the HSO.
In fact in the code, all the various output routines call the same subroutine to write to the HSO queue.
On the A9L, this is a sequential injection setup, so the HSO outputs are quickly filled up - 8 injectors and SPOUT, so things like idle control, fan control etc are relegated to low speed and bidirectional (also low speed) ports.
The low speed out port (Register 2) has bit 7 used for fuel pump, and bit 6 used as a 'CPU OK' watchdog on every listing I've seen so far....
The CPU OK has to be flipped at regular intervals, otherwise the box goes into 'limp home' mode, which I think is an analogue backup circuit, with no CPU.
The fuel pump drive timeout (i.e. no PIP pulses) is typically driven from the 'IO_Timer overflow' interrupt, which will occur 6 times a second on a 15 Mhz crystal. Most fuel pumps run 1 second without any PIP pulses.
In fact in the code, all the various output routines call the same subroutine to write to the HSO queue.
On the A9L, this is a sequential injection setup, so the HSO outputs are quickly filled up - 8 injectors and SPOUT, so things like idle control, fan control etc are relegated to low speed and bidirectional (also low speed) ports.
The low speed out port (Register 2) has bit 7 used for fuel pump, and bit 6 used as a 'CPU OK' watchdog on every listing I've seen so far....
The CPU OK has to be flipped at regular intervals, otherwise the box goes into 'limp home' mode, which I think is an analogue backup circuit, with no CPU.
The fuel pump drive timeout (i.e. no PIP pulses) is typically driven from the 'IO_Timer overflow' interrupt, which will occur 6 times a second on a 15 Mhz crystal. Most fuel pumps run 1 second without any PIP pulses.
TVR, kit cars, classic cars. Ex IT geek, development and databases.
https://github.com/tvrfan/EEC-IV-disassembler
https://github.com/tvrfan/EEC-IV-disassembler
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